1. Field
Example embodiments of the inventive concepts relate to a stacked semiconductor package, for example, to a stacked semiconductor package including thermal vias.
2. Background
Recently, a stacked semiconductor package is fabricated by sequentially stacking a lower semiconductor package and an upper semiconductor package to achieve high integration. The lower semiconductor package includes a lower chip stack structure on a lower printed circuit board. The upper semiconductor package includes an upper chip stack structure on an upper printed circuit board. The lower and upper chip stack structures each includes sequentially stacked semiconductor chips. Accordingly, the stacked semiconductor package includes the lower printed circuit board, the lower chip stack structure, the upper printed circuit board, the upper chip stack structure, which are sequentially stacked.
In this case, since the stacked semiconductor package has the upper printed circuit board between the lower chip stack structure and the upper chip stack structure, a process for achieving high integration is limited. This is because the upper printed circuit board is disposed between the lower chip stack structure and the upper chip stack structure, so that it is difficult to reduce the thickness of the stacked semiconductor package. In addition, since the stacked semiconductor package has the lower chip stack structure between the lower printed circuit board and the upper printed circuit board, a process for achieving high integration is limited. This is because as the number of the stacked semiconductor chips of the lower chip stack structure increases, the process defective rate increases between the lower printed circuit board and the upper printed circuit board. Thus, the stacked semiconductor package has poor process tolerances with respect to high integration. This makes it difficult to implement multi-function trend in stacked semiconductor packages.